1. Field of the Invention
The present invention relates to a duty cycle generator and power converter, and more particularly, to a duty cycle generator and power converter having better noise susceptibility.
2. Description of the Prior Art
An electronic device includes various components, each of which may operate at different voltage levels. Therefore, a direct current (DC) converter is definitely required to adjust (step up or down) and stabilize the voltage level in the electronic device. Originating from a buck (or step down) converter and a boost (or step up) converter, various types of DC converters are accordingly customized to meet different power requirements. As implied by the names, the buck converter is utilized for stepping down a DC voltage of an input terminal to a default voltage level, and the boost converter is for stepping up the DC voltage of the input terminal. With the advancement of modern electronics technology, both of the buck converter and the boost converter are modified and customized to conform to different architectures or to meet different requirements.
For example, please refer to FIG. 1, which is a schematic diagram of a power converter 10. The power converter 10 is used for converting an input voltage VIN to an output voltage VOUT, the power converter 10 includes a drive stage circuit 11, an output stage circuit 12, a clock generator 13, a duty cycle generator 14, a feedback circuit 16 and a compensation circuit 18. The drive stage circuit 11 includes a high-side switch HS, a low-side switch LS and front-end drivers 15 and 17, the drive stage circuit 11 may respectively utilize the front-end drivers 15 and 17 to transfer the duty cycle signal SDUTY generated by the duty cycle generator 14 into front-end drive signals UG and LG to respectively turn on or off the high-side switch HS and the low-side switch LS. The high-side switch HS and the low-side switch LS may be switched between turning on and off in turns, i.e. the high-side switch HS is turned on while the low-side switch LS is turned off, and the high-side switch HS is tuned off while the low-side switch LS is turned on, such that an output terminal of the drive stage circuit 11 may generate a switch signal PHASE to the output stage circuit 12. The output stage circuit 12 includes an inductor L and an output capacitor CLOAD, the output stage circuit 12 is coupled between the output terminal of the drive stage circuit 11 and a ground. The inductor L of the output stage circuit 12 may be charged and discharged according to the switch signal PHASE outputted by the output drive stage circuit 11, such that the output stage circuit 12 may output voltage VOUT with a predefined voltage value by cooperating with the voltage stabilization function of the output capacitor CLOAD.
The feedback circuit 16 includes an adjustment unit AD and a comparator OPA. After the adjustment unit AD transfers the output voltage VOUT into the feedback voltage FB. The comparator OPA may compare the feedback voltage FB with a reference voltage REF to generate a comparison signal COMP to the duty cycle generator 14, such that the duty cycle generator 14 may generate the duty cycle signal SDUTY according to the comparison signal COMP and a clock signal CLK generated by the clock generator 13. The feedback voltage FB is equal to K times the output voltage VOUT, wherein K may any constant value. The compensation circuit 18 includes capacitors C1 and C2 and a resistor R, the compensation circuit 18 is used for compensating a frequency response of the power converter 10 to ensure a stable operation of the power converter 10.
Please refer to FIG. 2, which is a schematic diagram of the duty cycle generator 14 shown in FIG. 1. The duty cycle generator 14 includes a comparator 25, inverters IV1, IV2 and IV3, an SR-latch 21 and a triangle-wave generator 22. Connections of the elements in the duty cycle generator 14 are shown in FIG. 2, the clock generator 13 may output the clock signal CLK to the triangle-wave generator to trigger the triangle-wave generator 22 to generate a triangle-wave signal RAMP. When the comparison signal COMP is greater than the triangle-wave signal RAMP, the comparator 25 may output a high voltage. When the comparison signal COMP is less than the triangle-wave signal RAMP, the comparator 25 may output a low voltage. Thus, when the clock signal CLK is at a high voltage, a set input terminal of the SR-latch 21 is at a high voltage, such that the duty cycle signal SDUTY is set to be a high voltage to turn on the high-side switch HS. When the clock signal CLK is at a low voltage and the comparator 25 is at a high voltage, a reset input terminal of the SR-latch 21 is at a high voltage to reset the duty cycle signal SDUTY to be a low voltage to turn off the high-side switch HS. As a result, the duty cycle generator 14 may generate the duty cycle signal SDUTY switching between high and low voltages to control the high-side switch HS and the low-side switch LS to be turned on and off.
An ideal triangle-wave signal RAMP may have a regular triangle-shape, however, the triangle-wave signal RAMP may not have the ideal triangle-shape in practice. A voltage integrator inside the triangle-wave generator 22 is controlled by the clock signal CLK to perform charging and discharging, during an early rising edge of the clock signal CLK, the integrator may occur a transient state response due to an inner parasitic inductor of the triangle-wave generator 22, which may cause ripples or small glitches shown in an early rising edge of the triangle-wave signal RAMP. Please refer to FIG. 3, which is a schematic diagram illustrating waveforms of a non-ideal triangle-wave signal RAMP, the ideal comparison signal COMP, the duty cycle signal SDUTY and the clock signal CLK. As shown FIG. 3, if a voltage level of the comparison signal COMP is relative low, even a small amount of ripple may cause the non-ideal triangle-wave signal RAMP to oscillate around the comparison signal COMP, which may lead to the duty cycle generator 14 generating the wrong duty cycle signal SDUTY. In other words, the power converter 10 is easily influenced by the non-ideal triangle-wave signal RAMP to generate the wrong output voltage VOUT when the duty cycle is relative low.
Furthermore, in practice, the power converter 10 may be integrated into a power integrated circuit (IC) through a semiconductor manufacturing process. However, capacitances of the compensation capacitors C1, C2 are usually nano Farads and a resistance of the resistor R is usually mega Ohm, which may not be integrated into the IC due to a limitation of the semiconductor manufacturing process. As a result, the compensation circuit 18 is normally disposed outside the power converter 10. Therefore, the comparison signal COMP is susceptible to noises from outer elements, which may cause the duty cycle signal SDUTY generated by the duty cycle generator 14 to be influenced by the noises leading to the power converter 10 generating the wrong output voltage VOUT.
Specifically, please refer to FIG. 4, which is a schematic diagram illustrating waveforms of the ideal triangle-wave signal RAMP, the comparison signal COMP influenced by the noise, the duty cycle signal SDUTY and the clock signal CLK. As shown in FIG. 4, the ideal triangle-wave signal RAMP has a regular triangle-shape, the comparison signal COMP is influenced by the noise (glitch) to have an irregular waveform, the comparison signal COMP influenced by the noise oscillates around the triangle-wave signal RAMP. In other words, since the comparison signal COMP oscillates around the triangle-wave signal RAMP, the comparator 25 output the swinging comparison result OUT, such that the SR-latch 21 outputs the swinging duty cycle signal SDUTY to the power converter 10, which causes the power converter 10 to generate the wrong output voltage VOUT accordingly. Noticeably, if a voltage level of the comparison signal COMP is relatively low, even a small amount of noise might cause the duty cycle generator 14 to generate the wrong duty cycle signal SDUTY. In short, the power converter 10 may be easily influenced by the noise to generate the wrong output voltage VOUT when the duty cycle is relative low.
Therefore, in order to solve the situation that the power converter 10 operating in a low duty may generate the wrong output voltage VOUT due to a non-ideal response or noises from the outer elements, there is a need to improve the prior art.